The present disclosure relates to the design of integrated circuits, and more specifically, to structures and methods for parallel testing of large numbers of devices.
An integrated circuit (IC) is a semiconductor device containing many small, interconnected components such as diodes, transistors, resistors, and capacitors. These components function together to enable the IC to perform a task, such as control an electronic device, or perform logic operations. ICs are found in computers, calculators, cellular telephones, and many other electronic devices.
ICs and other semiconductor devices are fabricated on small rectangles, known as “dies,” which are filled with multiple layers of the components, such as transistors, resistors, and capacitors, during the fabrication process. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS and as well as metal insulator semiconductor (MIS) technologies are currently among the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
Various processes are performed on semiconductor substrates in manufacturing integrated circuit products. A manufacturing error in one of the components may render an IC or semiconductor device incapable of functioning properly. For example, consider a memory device containing several ICs. If a transistor within one of the ICs fails to function properly, the memory device may produce memory errors. Therefore, when integrated circuits are formed, tests are performed to determine the correctness in the operation of the circuits.
Manufacturers generally perform various tests to determine the effects of the various processes on the performance and reliability of the circuits. Various quality or performance criterions may be used in determining whether the integrated circuits meet quality standards. In particular, conventional Time Dependent Dielectric Breakdown (TDDB) test can typically only test a maximum of 24 devices in parallel from the same test macro at the same time. In addition, limited by the number of source measurement units (SMUs), the real testing is only limited to eight devices in parallel. In advanced technology node, die-to-die variations become the largest TDDB performance limiter. Thus, more data points need to be collected within each die to separate intrinsic TDDB performance from global variations. No cost effective test implementation (structure and test system) is available for massive parallel TDDB test at individual die level.